1. Field of the Invention
The present invention relates to a frequency synthesizer for synthesizing radio frequency signals, and more specifically to a fractional-N frequency synthesizer having a sigma-delta modulator that can enhance a frequency resolution of the output frequency of the frequency synthesizer without increasing input bits of the sigma-delta modulator.
2. Description of the Related Art
The demand for wireless real time multimedia data services is increasing. Consumers want high speed internet access via mobile devices, and also desire to upload or download multimedia data via mobile devices.
CDMA (Code Division Multiple Access) 2000 can provide high speed data service at 144 kbps which is used in the CDMA/PCS (Personal Communication System). Frequency synthesizers are an essential part of any modern communication system. Frequency synthesizers generate clock and oscillator signals needed for up and down conversion. Today's communication standards demand both high frequency accuracy and fast frequency settling.
Frequency synthesizers used in high speed data communications generally must satisfy setting time less than 500 μs, 10 KHz of frequency resolution, and phase noise less than −135 dBc/Hz at 1 MHz offset frequency. To satisfy a setting time of less than 500 μs, in a frequency synthesizer, the loop bandwidth of a PLL (Phase-Locked Loop) must be at least 10 KHz.
Generally, a mobile communication system such as CDMA or PCS employs an integer-N frequency synthesizer, for generating output frequencies that are integer multiples of a reference frequency. The integer-N frequency synthesizer has structural limitation in that the channel bandwidth of the integer-N frequency synthesizer is the same as the reference frequency. The channel bandwidth of the frequency synthesizer is referred to as a “frequency resolution” for selecting an exact channel. In a mobile communication system such as CDMA/PCS that have relatively small channel bandwidths of 30 kHz/10 kHz, respectively, a loop bandwidth of the CDMA/PCS should be much less than 30 kHz/10 kHz, respectively. Thus, the integer-N frequency synthesizer is not alone sufficient in a mobile communication system that requires settling time less than several milliseconds.
Thus, the conventional mobile communication system such as CDMA or PCS employs not only the integer-N frequency synthesizer but also a fractional-N frequency synthesizer. The fractional-N frequency synthesizer employs a sigma-delta modulator. A sigma-delta modulated signal output by the sigma-delta modulator controls the instantaneous frequency division modulus of a phase-locked loop used in fractional-N frequency synthesis. The sigma-delta modulator should be designed to have a frequency resolution of several Hz because the sigma-delta modulator should satisfy channel frequency spacing of multi-band.
Conventionally, in order for the sigma-delta modulator to have a frequency resolution of fewer Hz, input bits of input signal of the sigma-delta modulator are increased, and thus hardware size of the sigma-delta modulator may be increased.
When the input bits of the conventional sigma-delta modulator are decreased (in order to decrease the hardware size of the sigma-delta modulator), the frequency resolution may be decreased (i.e. the spacing between channel frequencies may become wider), and the sigma-delta modulator will not satisfy channel frequency spacing of multi-band communication.